Akihiro Itou is a staff engineer at Panasonic Smart Factory Solutions, currently involved in the development of plasma dicing equipment and processes. In 2001, he joined Matsushita Electric Industrial Co., Ltd. (now, Panasonic Co., Ltd.). Since then, he has been engaged in R&D activities and worked in development of Fiber Bragg Grating processes for ultra high speed optical fiber communication and photovoltaic device processes for concentrator photovoltaics. He received a M.S. degree in material physics from Osaka University, Japan.
Vertical-cavity surface-emitting lasers (VCSELs) are now key optical sources in gigabit ethernet, high-speed optical-area networks, and computer links because of the advantages they offer, such as low threshold current and a small structure. During conventional blade dicing of VCSELs fabricated on gallium-arsenide (GaAs) substrates, GaAs wafers are fragile and chipping or edge cracks can easily occur. Hence, in the case of conventional saw processes, generally the kerf must be wider and the blade feed speed must be slower in order to avoid device damage due to chipping or edge cracks, which cause limitation of productivity. Plasma dicing has been proposed as a new wafer singulation method. The plasma dicing process is a technology to dice the entire wafer into chips at once . As the wafer is processed using a chemical reaction by plasma, plasma dicing does not cause any physical damage to chips, regardless of the wafer thickness. Thus, the plasma dicing process eliminates chipping and cracks at the edge of chips. In addition, the number of chips which can be taken from one wafer are able to be increased by reducing kerf width, which is approximately the same as the opening width of photo resist during the lithography process before plasma dicing. In this report, we apply plasma dicing to VCSEL on GaAs substrate and demonstrate GaAs dicing, with no chipping at the edge of VCSELs or surface particles.